A CUSTOMIZABLE SoPC ARCHITECTURE FOR GA BASED ON COMPLETE HARDWARE EVOLUTION

A Genetic Algorithm (GA) is a computer based search optimization technique that uses the Darwinian “Theory of Evolution” as a model for finding exact and approximate solutions. GAs belong to a large family of heuristic algorithms called Evolutionary algorithms (EA) which are being increasingly utilized for solving complex optimization and search problems. The large computation time consumed by a GA implemented in software makes it unsuitable for real time applications. This hurdle is overcome by shifting the implementation to hardware, which drastically speeds up the time factor, thus presenting a scope for real time applications. Major issues to be addressed in hardware implementation are silicon utilization, scalability, providing flexibility and reduced computational delays. This work presents a customizable Complete Hardware Evolution (CHE) based GA architecture. Along with the generic modules for the genetic operators of the GA, modules named Flush and Replace Memory (FRM), Memory Module (MM), and a sorting module form the main components of this architecture. These modules can facilitate System on Programmable Chip (SoPC) implementation for different applications of GA. The coding is done using Verilog Hardware Description Language (HDL) and simulated using Xilinx ISE 9.1i simulator. Each module is separately simulated and synthesized for a Commercial Off The Shelf (COTS) Field Programmable Gate Array (FPGA). The resource utilization and the critical path delay of the modules are evaluated and presented for Xilinx Virtex – 4 FPGA.